`timescale 1ns / 1ps

module ExcReg(
    input clk,
    input reset,
    input thisExc,
    input [4:0] thisExcCode,
    input prevExc,
    input en,
    input [4:0] prevExcCode,
    output reg [4:0] ExcCode,
    output reg exc
    );

    initial {ExcCode, exc} <= 0;

    always @(posedge clk) begin
        if(reset) {ExcCode, exc} <= 0;
        else if(en)begin
            if(prevExc)begin
                exc <= prevExc;
                ExcCode <= prevExcCode;
            end
            else begin
                exc <= thisExc;
                ExcCode <= thisExcCode;
            end
        end 
        else ;
    end

endmodule
